As the dimensions of integrated circuit devices continue to decrease, the time delay for the propagation of a signal between multiple transistors (i.e., propagation delay) has become an increasingly important parameter in determining device performance. Propagation delay is proportional to the product of the resistance of a metal interconnect line (R) and the capacitance of the interlevel dielectric insulation material (C) (also referred to as RC delay). Thus, to minimize propagation delay, it is beneficial to incorporate an insulating material with a low dielectric constant material in combination with a high conductivity metal (or low resistivity metal). Low-k dielectric (LKD) materials (k<3.0), such as organosilicate glass (OSG), organosilicate glass (OSG), tetraethylorthosilicate (TEOS), fluorinated silica glass (FSG) and carbon-doped oxides, are also gaining interest as alternatives to silicon oxide (k=3.8-4.0). To obtain lower dielectric values, the LKD material can contain an interconnected nanoporous structure, which entraps air (k=1) to lower the overall k value of the bulk LKD. Likewise, copper (Cu) has gained considerable interest as a metal for interconnect lines, as an alternative to the more conventional aluminum (Al) interconnect metal (R=3.0-5.0 μΩ-cm), because of its lower resistivity value (R<2 μΩ-cm).
Because copper does not readily form volatile by-products, conventional or subtractive etching techniques are inadequate. Thus, damascene manufacturing processes are necessary to form patterned copper interconnect lines, processes that involve depositing conductive material in previously patterned openings (e.g., trenches or vias). Thus, damascene processing necessitates the etching of previously patterned openings in the LKD material. This is performed by patterning openings in a mask layer, such as photoresist, on a dielectric layer in the shape of a trench or via, followed by wet or dry etching. However, the etching, ashing or cleaning of LKD materials can potentially damage the LKD material.